Showing posts with label FSM. Show all posts
Showing posts with label FSM. Show all posts

Friday, 21 June 2013

Applying State Design Pattern to Code an FSM


A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model of computation used to design both computer programs and sequential logic circuits. The behavior of state machines can be observed in many devices in modern society which perform a predetermined sequence of actions depending on a sequence of events with which they are presented. 

A programmer often needs to model states of classes implementing such real life behavior. States of  a class can be implemented using some class variables denoting the a particular state the class is in. While handling the events the class is sensitive to, a check can be done to find the current state and appropriate action can be taken. For example 'if(state ==ON) do this else do that'. But this approach gets complicated if the number of states or events to which class has to react increase.